1. Field of the Invention
This invention relates to digital computer systems and more particularly to a system for the faster performance of virtual look-ahead memory operations.
2. Description of the Prior Art
Virtual memory operations in most computers are done in two parts. First, a translation process is required to translate each virtual address into a corresponding real address and, second, the required memory operation is performed with this translated address. As a result, the total time required for a virtual memory operation is typically equal to the sum of the translation time of the virtual address and the time that it takes to perform the actual memory operation.
To reduce this total time to perform a virtual memory operation, an improved address translation apparatus for translating virtual addresses into real addresses was proposed, as described in the U.S. Pat. No. 4,513,371 of John A. Celio, which patent is assigned to NCR Corporation, the assignee of the present invention.
FIGS. 1 and 2 of the drawings, respectively, illustrate a block diagram of the apparatus of the above-noted U.S. Pat. No. 4,513,371 and a functional diagram of how the various components of a virtual address are utilized in that patent during an address translation. As shown in FIG. 1, a 32-bit processor-memory bus 21 interconnects a processor element 23, an address translation element 25 and a memory interface element 27. The processor element 23 generates a virtual address and the address translation element 25 converts the virtual address to a real address. The memory interface element 27 supplies timing control signals and memory address inputs to a memory or DRAM (dynamic random access memory) array 29 to access data during fetch and store operations. The apparatus of FIG. 1 allocates its virtual memory into pages of information. As a result, a first portion of the virtual address from the processor element 23 is used to indicate the "displacement" (FIG. 2) or relative address within each page, while a second portion of the virtual address is used to indicate the "virtual page number" (FIG. 2) within the virtual memory of the apparatus of FIG. 1.
The virtual page number portion is derived from the most significant bits of the virtual address, while the displacement portion is derived from the least significant bits of the virtual address. The virtual page number portion is applied to the address translation element 25 for an address translation into a second portion of a real address. The displacement portion is actually a first portion of the real address and therefore requires no address translation. As a result, this displacement portion of the real address is applied to the memory interface element 27 to enable the element 27 to start the RAS (row address strobe) access portion of the real memory access of the DRAM 29. Upon completion of the address translation of the virtual page number portion, the translated remaining portion of the real address is applied to the memory interface element 27 which then generates signals to complete the CAS (column address strobe) access portion of the real memory access of the DRAM 29.
Thus, the apparatus of U.S. Pat. No. 4,513,371 decreases the virtual memory access time by minimizing the address translation time. Such minimization of the address translation time is the result of not translating virtual address bits that are also real address bits and of commencing memory access by using the available real address bits as soon as they become available. The time saved by such a decreased access time is equal to the RAS to CAS minimum delay requirement for the particular DRAM that is employed in the apparatus.